This invention relates to Current Mode Logic (CML) devices, and in particular to a high-speed, low component count, CML Exclusive NOR gate.
FIG. 1 illustrates an exclusive OR-NOR gate of the CML type, together with its truth table, which is a derivative of Emitter Coupled Logic (ECL), and which requires seven active elements and two threshold voltage sources VT-1 and VT-2.
FIG. 2 is a typical exclusive OR gate of the Transistor Transistor Logic (TTL), utilizing eleven active elements. When node A is HIGH, and node B is LOW, then transistor Q7 conducts, and the Y output is HIGH. When node A is LOW, and node B is HIGH, then transistor Q8 conducts, the Y output is HIGH. However, if both nodes A and B are either HIGH or LOW together, then neither transistor Q7 nor Q8 can conduct, and therefore the Y output is LOW. This operation is due to the cross coupled arrangement of transistors Q7 and Q8. Typical of TTL type circuitry, the voltage swings are greater than CML, the transistors saturate, and thus the speed of TTL is less than the speed of CML type logic devices.
It is recognized, therefore, that in LSI applications, there is a need for a minimum size exclusive OR function in the CML type circuitry, and it is, therefore, an object of this invention to provide a CML type exclusive NOR gate, which is faster and utilizes a lower number of active devices than in the prior art, and eliminates the need for additional threshold voltage sources as in the prior art.